Asynchronous Transfer Mode (ATM) networks allow a large number of data flow paths or Virtual Channels (VCs) to be statistically multiplexed over a common link. A high speed ATM connection allows a host end-point device, for example, a computer, to have a large number of simultaneous virtual channels sharing bandwidth of the common link. A challenge in implementing the large number of virtual channels is to achieve specified Quality of Service (QOS) for each virtual channel independent of other virtual channels. The challenge is compounded when a mix of virtual channels with differing requirements for the QOS have to be satisfied.
In order to efficiently accommodate the differing QOS requirements of multiple virtual channels, a scheduler in an end-point device should be able to respond quickly to changes in transmission rates on the individual virtual channels. This is required, for example, for the Variable Bit Rate (VBR) and the best effort or Available Bit Rate (ABR) classes of service. The scheduler should also be able to dynamically adjust the scheduling when new virtual channels are added or old ones are removed or existing virtual channels stop or start sending data temporarily. In addition, the scheduler should also minimize the jitter, that is, changes in cell rate. This is important because ATM switches, which receive streams of cells generated by the scheduler, continuously monitor each VC using a leaky bucket algorithm or Generic Cell Rate Algorithm (GCRA) to check if the switch is adhering to the traffic contract. In the event the leaky bucket overflows, the cells can potentially be dropped by the switch. Accordingly, the scheduler should protect against this by minimizing the jitter. In case of constant bit rate (CBR) channels, a buffer is required at the receiving end to remove the jitter and smooth the incoming flow of cells. Increased jitter will then require a larger buffer.
Scheduling schemes have been proposed in the prior art for scheduling VCs within a switch and within an end-point. Heretofore, these schemes have been unable to meet the requirements necessary for efficient implementation of multiple virtual channels having various transmission rates and differing QOS guarantees. Accordingly, there is a need for a scheduling mechanism capable of implementing specified transmission rates for each virtual channel independent of other virtual channels, wherein the virtual channels include a mix of differing QOS requirements. U.S. patent application Ser. No. 08/580,470, now U.S. Pat. No. 5,751,709 the parent of the present application addresses this need.
A scheduler in an end-point device should also be able to accommodate a low latency QOS requirement of an individual virtual channel. One application where low latency is of concern is the use of an ATM network to build a parallel processing system where individual workstations act as nodes and the ATM network functions as the fabric for inter-processor communication. In this ATM network application it is necessary to have a lock manager, whose messages are typically short and infrequent, for locking a resource when it is accessed by one processor, thereby preventing access to the resource to more than one processor at a time. Since a principal objective for using the ATM network for parallel processing is the potential for increased throughput, the ATM network is a stable fabric. However, the increased throughput is achieved at the expense of high latency. With respect to the lock manager, this cost is very serious as end points are prevented from accessing a resource until it is released by the lock manager operation. Thus reducing latency for the lock manager is critical to realizing high throughout.